Principal Duties Responsibilities:
Design the analog layout in power management products. Design includes low & high voltage CMOS layout design DRC, LVS verification.
Finish analog IC top layout DRC, LVS verification independently.
Knowledge, Skills, Abilities Required:
-BSEE with knowledge in analog IC layout design.
-At least 5 years working experience in CMOS process
-Good knowledge in design of IC analog top block layout.
- Able to work in a team with good written communication skills.
-Able to finish project layout independently.
- Preferably with high voltage BCD process experience.
