专业要求：
1． Analog Mixed signal IC custom layout design.
2. Chip/Top level floorplanning integration (Senilayout engineer).
职位描述：
1. Familiar with Cadence design environment (Virtuoso) Verification such as MentCalibre.
2. Industry experience in layout of analog mixed-signal ICs, such as high speed (GHz) analog circuits including PLLs high-speed I/Os, etc.
3. Good understanding of design rules, device matching, isolation techniques.
4. Basic understanding of semiconductdevices IC process manufacturing.
5. Experience in top level floorplanning integration is a plus.
6. BS degree in Electrical Engineering Microelectronics.
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