Summary
We are looking to onboard a high performance FPGA IP engineer fFW development.
This engineer will work closely with other engineers from HWTE teams multi-functional teams from worldwide. He/She will also review Vendor/Contract IP programming
to accomplish IP development issue triage.
Description
You will be working on an innovative platform join a creative passionate HW/FW developer team to be part of great innovation excellence. You will be working on an advanced in-house design of embedded system as instrumentation controller built with Xilinx Zynq SoC. The FPGA IP engineer will be in charge of developing validating customized IPs, also expected to provide support to project team when on-the-field issues occur. The candidate needs to have profound experience on IP development, with good understanding of Verilog HDL programming HW design.
Job scope will be part of below description:
• Work closely with hardware architects system engineers to define IP
requirements
• Design, develop, verify FPGA-based IP cores finternal customized applications in Verilog/VHDL
• Develop testbenches simulation environments ffunctional verification
• Optimize IP farea, speed, power based on application constraints
• Perform simulation, synthesis, place-and-route, timing closure
• Integrate IP cores larger FPGA SoC systems using standard bus protocols
• Debug hardware using simulation tools, logic analyzers, in-system debugging tools
• Maintain enhance a reusable library of IP blocks with clear versioning documentation
• Support FPGA bring-up, lab validation, system-level testing
• Collaborate with software firmware teams to ensure seamless integration
• Design Validation documentation with presentation in enterprise environment.
• VendIP review guidance
Qualifications
• BS EE/CS/CE above
•Minimum 3 years of relevant work experience as IP developer, preferably on platform development, data acquisition, instrumentation development
•Proficiency in Verilog HDL programming, synthesis, place&route, simulation, timing constraint performance optimization.
•Proficient in using FPGA development tools (Vivado, Quartus, ModelSim, Synplify, etc).
•Knowledge of AXI, Avalon, Wishbone, other standard IP interfaces.
•Experience with testbench creation, debugging have strong problem solving
skills.
•Ability to write clear documentation fIP cores user interfaces.
•Experienced in logic design of digital I/O protocol, FSM, DSP etc..
•Familiar with USB, SPI/I2C, SWD, UART, Serdes, FIR.
•Familiar with any mainstream programming/script language (C/Python).
•Familiar with version control system (git SVN).
•Adequate written verbal Chinese/English skill.
•Fast learner innovative.
•Self-driven passionate. Able to perform under tight schedule.
Preferred
•Understanding of embedded systems, SoC, hardware/software co-design.
•Experience of Xilinx Zynq Intel Altera SoC platform development.
•Experience of SystemVerilog UVM fFPGA simulation.
•Experience of C++ programming
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