职场数据点评 让职场人少走弯路
公司 工资 行业 专业 工作 排行榜 找客户
工作 |
工作 公司 工资 专业
人气  13万   |   粉丝  38   |   喜欢  44   |   反馈  29 认领公司

高性能模拟和混合信号半导体公司

芯源系统 pd 招聘(工资待遇要求)

芯源系统 pd 薪酬区间: 20K - 50K,其中100%的岗位拿¥20-50K以上
芯源系统 pd 薪酬区间:20K-50K,最多岗位拿 50K以上,取自近一年 13 个相关岗位,截至 2026-06-01
¥20-50K以上
100%的岗位拿

说明:岗位平均工资是以企业发布的招聘岗位为分析依据,建议结合职位类型及学历地区经验等查看。

芯源系统 pd 历年工资变化

说明:数据取决于当年在线职位薪酬样本,并不能完全代表企业内部真实情况。仅供参考。

招聘学历要求:硕士最多

芯源系统 pd 需要什么学历? 硕士占比最多,占100%

按学历统计

芯源系统 pd 工资按学历统计,硕士工资¥41.9K。

招聘经验要求:不限最多

芯源系统 pd 需要什么经验? 不限占比最多,占38.5%,5-10年占38.5%,1-3年占23.1%

按经验统计

芯源系统 pd 工资按经验统计,1-3年工资¥25.0K,5-10年工资¥44.0K。

芯源系统 pd 招聘地区:主要分布在成都,杭州

芯源系统 pd 在哪些城市有办公地点? 主要分布如下:成都占69.2%,想知道其他城市分别占比多少?请点击该模块查看,统计依赖近一年招聘职位,仅供参考。

芯源系统 pd 历年需求趋势

芯源系统 pd 历年招聘量变化

芯源系统 pd 是做什么的

取自芯源系统近一年相关招聘职位
  • Digital Design Engineer Lead (DDR5 SPD HUB)

    成都 | 硕士以上 | 2025-12-18
    40-65k
    Summary:
    SPD Hub Digital Designer Lead will lead the design development, design implementation, verification of digital logic fDDR5 SPD Hub (Serial Presence Detect Hub) including register interface, control logic, security features, I3C/I²C communication modules. This position requires both technical leadership skills owning solid digital design fundamentals, familiarity with memory architecture, experience in RTL development chip integration while working closely with multi-disciplinary groups to drive design key aspects of SPD Hub products.
    RESPONSIBILITIES:
    • Participate in architecture definition micro-architecture design fDDR5 SPD Hub features.
    • Develop lead RTL (Verilog/SystemVerilog) fI3C, I²C, RCD/SPD-Hub related control logic, ECC/parity protection mechanisms.
    • Perform lead digital design verification/testcases using standard RTL/DV languages (Verilog, SV, UVM), strong documentation skills fspec/test plan documents.
    • Works closely with digital design team collaborate with analog/mixed-signal, DFT, physical design teams to support full-chip integration.
    • Work closely with firmware validation teams to ensure correct system-level behavior.
    • Solid knowledge of industry standard ASIC tools/flow fdaily work: Digital Simulators, synthesis tools, DFT, LEC, STA, etc
    • Participate in bring-up, validation, failure analysis fengineering samples.
    • Provide documentation including design spec, timing diagrams, integration guide.
    • Good written/verbal communication English skills strong team work/collaboration.
    REQUIREMENTS:
    • PhD MS degree with 10+ years of experience in digital ASIC design.
    • Experience with memory subsystem architecture, preferably DDR4/DDR5 SPD/RCD devices.
    • Experience with DDR5 SPD Hub RCD/PMIC product development.
    • Knowledge of I3C (MIPI) protocol, I²C/SMBus, SPD EEPROM behavior.
    • Experience with security logic, including encryption/authentication basics.
    • Strong knowledge of ASIC development process digital design techniques.
    • Experience with programming, scripting automation languages like Perl/TCL/Unix/Python C/C++
    • Executing tasks that hit project milestones
    • Knowledge/Experience with the following is a plus:
     embedded designs and/firmware development
     knowledge of power management industry/applications
     experience of mixed signal design
     I2C, I3C, SPI, USB, PMBUS/USB-PD
    更多
  • Digital Design Engineer Lead (DDR5 SPD Hub)

    成都-高新区 | 硕士以上 | 2025-12-18
    50-80万/年 򀀩
  • Digital Design Engineer Lead-DDR SPD Hub

    成都-郫都区 | 硕士以上 | 2026-02-14
    40000-65000 򀀩
  • Digital Design Engineer Lead (DDR5 SPD HUB)

    成都 | 硕士以上 | 2026-04-09
    40-65k 򀀩
  • Application Engineering Manager (DDR5, SPDHUB/TS focus)

    成都 | 5-10年 | 硕士以上 | 2026-04-14
    35-45k 򀀩
  • Application Engineer (DDR5, SPDHUB/TS focus)

    成都 | 1-3年 | 硕士以上 | 2026-04-14
    򀀩

成都 pd 招聘工资待遇

更多
成都 pd 工资多少?拿10-15K工资占比最多
K12教育
客服
由百度提供