Summary:
A SeniDigital Verification Engineer will define lead the development of the Digital Verification framework infrastructure of complex digital mixed-signal ICs utilizing leading edge technologies with industry standard ASIC tools. Products to be designed/verified may include power management, signal management mixed signal functions.
MPS products include: switching regulators, sensors, motcontrol, display drivers, audio amplifiers power management ICs ffast-growing portable non-portable markets such as notebooks, cell phones, telecom, digital camera, automobile network equipment.
RESPONSIBILITIES:
UVM System Verilog based Digital Verification environment definition development.
VIPs standardization, definition, development documentation.
Define VIP’s integration the Project’s Digital Verification environment.
Digital Verification Metrics definition fRTL Gate-Level Verification.
Test Plan definition development.
Digital Verification Automation Scripting.
Regression’s infrastructure definition, development management.
Close interaction with SeniDigital Analog Designers to develop VIP models.
Lead the Digital Verification Team.
Lead Supervise Digital Verification Tasks of multiple projects.
Review Digital Verification Metrics Results of multiple projects.
Define design Digital Verification Top-Level Tests.
Analyze debug test results, code coverage functional coverage.
Digital Verification estimation, planning scheduling to meet tape-out dates.
REQUIREMENTS:
PhD/MS in Electrical Engineering with emphasis in Digital Design/VLSI coursework.
5+ years of strong experience in both RTL Gate-Level Verification.
Proficient in Digital Verification Industry Languages (UVM, System Verilog) Standards.
Proficient Level in DV skills areas: Constraint random tests, SV assertions, coverage metrics, analog digital DV modelling, DV test plans, regression analysis reports, UVM DV Agents (Monitor, Driver, Scoreboard), etc.
Solid knowledge experience working through the entire Digital Design Flow: Specification definition, RTL Verification, Synthesis, P&R, Gate-Level Verification, Power Estimation, ATPG Generation Simulation, AMS Sims, etc.
Excellent Knowledge & Use of industry standard ASIC tools/flow fdaily work: Digital Simulators, synthesis tools, DFT, LEC, STA, etc.
Excellent scripting automation skills using TCL, Python C/C++.
Leadership skills to technically guide the DV Team mentJr. DV Designers.
Good written/verbal communication skills strong team work/collaboration.
Knowledge/Experience with the following is a plus:
oEmbedded designs and/firmware development
oKnowledge of power management industry/applications
oI2C, I3C, SPI, USB, PMBUS
oGitLab
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